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OUTPUT GLITCH SUPPRESSOR CIRCUIT FOR HIGH-SPEED STATIC RAMs

IP.com Disclosure Number: IPCOM000035402D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Pelella, AR: AUTHOR

Abstract

Disclosed is a method to prevent output glitches from occurring during a read operation in high-speed static random-access memories (SRAMs) that employ voltage-sensing amplifiers.

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OUTPUT GLITCH SUPPRESSOR CIRCUIT FOR HIGH-SPEED STATIC RAMs

Disclosed is a method to prevent output glitches from occurring during a read operation in high-speed static random-access memories (SRAMs) that employ voltage-sensing amplifiers.

As SRAMs get faster, the characteristics of the output waveform during the "Data Invalid" time (the time between the chip becoming

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active and the arrival of the data at the output) has become very important to the actual performance at the system level. For example, any glitches occurring during this time could cause reflections on system wiring and lengthen the actual access time of a chip seen by the system.

When a bit line is selected, transient voltage differentials can appear due to the large transient charge up currents. SRAMs that have amplifiers that sense bit line voltages can therefore send glitches to the output drivers before the actual data arrives on the bit lines.

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In order to prevent output glitching, the output latch must not be released until the new data is about to become available. Therefore, the selection of the bit lines, which occurs just prior to the new data becoming available, is a perfect delay for the output latch to be triggered by. Fig. 1 shows a block diagram how the bit line selection is used as the "output latch release" delay stage.

The diagram in Fig. 1 shows an "OR" function connected to the bit lines. Its output is connected to the latch release. Therefore, wh...