Browse Prior Art Database

Control of Time Delay Generation for Elements in a Daisy Chain

IP.com Disclosure Number: IPCOM000035403D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Schott, KP: AUTHOR

Abstract

This article describes a method for use in a microprocessor bus system to control the generation of a time delay in a chain of identical control elements equivalent to a time delay required in an associated chain of identical logical elements. The chains may be of arbitrary length.

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Control of Time Delay Generation for Elements in a Daisy Chain

This article describes a method for use in a microprocessor bus system to control the generation of a time delay in a chain of identical control elements equivalent to a time delay required in an associated chain of identical logical elements. The chains may be of arbitrary length.

The system arrangement is shown in block diagram in Fig. 1. It consists of the elements as follows: 1) A bus interface to a microprocessor-like bus system.
2) An unspecified number of universal asynchronous receivers/ transmitters (UARTs) or other logical elements, each of which can be the source of an interrupt request. Each UART can provide an interrupt address when signalled.
3) Control elements (CE) which provide individual UART controls. All CEs are identical logically, but one acts as a master and, in addition to controlling a UART, it also provides responses to bus interface requests for all UARTs. In par ticular, it indicates when a valid UART interrupt address is available on the UART data bus. The disposition of a CE (master or slave) is indicated by a function select (FSEL) pin.

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An interrupt sequence is shown in Fig. 2. It proceeds as follows: 1) The bus interface receives an interrupt request from one or more UARTs via the open collector interrupt request line. 2) The bus interface passes the interrupt request to the bus system. A CPU on the bus system will respond eventually and the bus interface will assert interrupt acknowledge (IACK). This will signal the UART to place the highest priority pending interrupt on the UART data bus lines. 3) IACK also signals the master CE to begin a timing sequence to determine when the interrupt address is valid. 4) More than one UART may have an interrupt pending. To determine the UART which will present the interrupt vector, an interrupt enable "daisy-chain" is used. This consists of serially connecting the interrupt enable in (IEI) and interrupt enable out (IEO) of each UART. In the scheme shown, UARTO has the highest priority and the UARTN the lowest. When IACK is asserted, the interrupt enable signal propagates from one UART to the next until a UART with a pending interrupt is found. At this point, the affected UART presents the interrupt address on th...