Browse Prior Art Database

Testability Design for Collector DOT Circuits

IP.com Disclosure Number: IPCOM000035404D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Wen, HJ: AUTHOR

Abstract

A method has been proposed for locating and analyzing faults/defects in integrated circuit chips which will be especially useful during the initial development and qualification of new, integrated circuit semiconductor devices. The proposal provides external control for previously inaccessible logic points so as to make the faults testable.

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Testability Design for Collector DOT Circuits

A method has been proposed for locating and analyzing faults/defects in integrated circuit chips which will be especially useful during the initial development and qualification of new, integrated circuit semiconductor devices. The proposal provides external control for previously inaccessible logic points so as to make the faults testable.

The truth table of a chain of blocks is shown in Fig. 1. An odd number of collector DOT circuits (CD19) was used to form a recirculating loop frequency (RLF). The pins A, D and 10, 20 are used to provide proper oscillation. Pins B, C are at logic 0. The possible input states of blocks B and C are 00, 01, 10.

A detail of the micro-logic blocks for one collector DOT circuit (CD19) is shown in Fig. 2. With the previous design B=C=0 the stuck- at-1 (s-a-1) fault of net 0110 and stuck-at-0 (s-a-0) of net 0210 cannot be detected due to missing input states 11. With the proposed design, B,C pins are connected directly to chip C-4 inputs. The required logic states: 11 can be obtained through C-4 inputs to pins B,C. Consequently, previously untested faults can be testable and higher testability is obtained.

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