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One-Cycle Execution Algorithm for the ICM Instruction

IP.com Disclosure Number: IPCOM000035417D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Robinson, JR: AUTHOR [+2]

Abstract

This is an improved algorithm to execute the IBM System/370 ICM (Insert Character Under Mask). This enables the execution of the same instruction in a single cycle for 15 out of 16 possible byte mask patterns. It uses a rotator, a 2-to-1 multiplexer and a byte selector to accomplish this task.

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One-Cycle Execution Algorithm for the ICM Instruction

This is an improved algorithm to execute the IBM System/370 ICM (Insert Character Under Mask). This enables the execution of the same instruction in a single cycle for 15 out of 16 possible byte mask patterns. It uses a rotator, a 2- to-1 multiplexer and a byte selector to accomplish this task.

The ICM instruction is formatted below and is executed by inserting bytes from contiguous locations starting at the second operand

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address, ((B2)+D2), into one of the general-purpose registers (GPRs) designated or selected by R1 under control of a byte mask, M3. The size of the second operand to be inserted is from 0 to 4 bytes. The byte mask, M3, indicates positions of bytes to be inserted in a GPR if a bit is one. It also indicates the number of bytes to be inserted from the total number of ones.

Here, B2 designates a GPR and D2 is a constant. (See Fig. 1.) The second operand address is calculated by adding the contents of a GPR (B2) and a constant (D2). (BF) is a hexadecimal operation code, and M3 is a four-bit byte mask.

Once an execution hardware fetches data from a memory, a basic operation to be done by the hardware is a rotate and an insert. Normally the execution hardware receives a byte of data in a right- justified form, rotates it in a proper position and inserts it. The hardware repeats the same process until requested data is exhausted.

However, assuming that maximum data required is received at one time and positions of two bytes to be inserted are contiguous, it requires the same rotate amount so that two bytes can be inserted at the same time, meaning that any contiguous bit pattern in a byte mask can be executed at the same time or in the same machine cycle.

A byte mask from the ICM instruction points to the location of bytes to be inserted and has four bits. From all possible combinations of four-bit patterns, the maximum number of sets of contiguous bit patterns is two. Therefore, the execution of the ICM instruction can be finished in two cycles after data is fetched from a memory if a basic operation, a rotate and an insert, is done in a cycle.

A schematic diagram of an execution hardware for ICM instruction is shown in Fig. 2 This consists of a rotator, a byte selector, two 1-to-1 multiplexers and other logic blocks. Here, the byte selector is divided into two 16-bit selectors, each of which selects different inputs. High-order two bytes of the output are selected from three sources, and low-order two bytes are from two sources. For high-order two bytes, multiplexer 1 is used to preselect one out of two sources so that in the next logic level, the high-order two byte selector can pick out one out of two.

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A typical operation can be illustrated using an example of two operands and a byte mask from an instruction. Let two operands be "ABCD" and "YYYY" in hexadecimal numbers and a byte mask be "0011" in a binary number. In this case, first...