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Browse Prior Art Database

Implicit Control of Operand Format in Multiplier

IP.com Disclosure Number: IPCOM000035420D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Gonzalez, MJ: AUTHOR [+2]

Abstract

Fig. 1 shows the situation in which this invention has been applied. The figure depicts the parts of the execution unit of a 32-bit processor relevant to this discussion. A two-ported Register File (RF) containing sixteen 32-bit general-purpose registers and a 32-bit ALU are interconnected through three busses (A, B and C). A hard-wired 16x16-bit multiplier has its operands mapped to the lower halves of R0 and R1 (two registers of RF). Each time R0 (or R1) is loaded, register R01 (or R11) of the multiplier become loaded with its sixteen least significant bits. A 32-bit product is available at the multiplier output for instructions like Multiply, Multiply-and-add, and Multiply-and-subtract. The product is not used in all other instructions.

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Implicit Control of Operand Format in Multiplier

Fig. 1 shows the situation in which this invention has been applied. The figure depicts the parts of the execution unit of a 32-bit processor relevant to this discussion. A two-ported Register File (RF) containing sixteen 32-bit general- purpose registers and a 32-bit ALU are interconnected through three busses (A, B and C). A hard-wired 16x16-bit multiplier has its operands mapped to the lower halves of R0 and R1 (two registers of RF). Each time R0 (or R1) is loaded, register R01 (or R11) of the multiplier become loaded with its sixteen least significant bits. A 32-bit product is available at the multiplier output for instructions like Multiply, Multiply-and-add, and Multiply-and-subtract. The product is not used in all other instructions. The Multiply instruction (M) passes the product through the ALU (no-op) and stores the result in a specified RF register. The Multiply-and-add instruction (MA) adds the product with the content of a specified register. The result replaces the content of a specified register (it can be the same or different). As the multiplier may take one instruction cycle to compute the actual product, the result is not available for the instruction following the R0 (or R1) Load instruction but to the instruction after the next instruction.

The following examples show how the technique is used. EXAMPLE 1: L R0,A R0 <==A L R1,B R1 <==B NOP M R3 RD <==A*B EXAMPLE 2: L R0,A R0 <== A L R1,B R1 <== B L R1,C R1 <== C M R3 R3 <== A*B 1st product available MA R4,R3 R4 <== (R3) + A*C 2nd product available

The problem when computing 32x32 multiplication with a 16x16-bit multiplier is that partial products involving signed and unsigned (positive) operands must be computed. Correction of result is required when the multiplier is restricted to operands in twos complement form. When the multiplier accepts both signed and unsigned operands (i.e., twos compleme...