Browse Prior Art Database

Measurement Tool for Instruction Mix in a Graphics Display

IP.com Disclosure Number: IPCOM000035421D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 51K

Publishing Venue

IBM

Related People

Callahan, RM: AUTHOR [+3]

Abstract

This article describes a measurement tool for instruction mix in a graphics display. The objective is to log the number of each opcode during the execution of a Display Program.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 30% of the total text.

Page 1 of 5

Measurement Tool for Instruction Mix in a Graphics Display

This article describes a measurement tool for instruction mix in a graphics display. The objective is to log the number of each opcode during the execution of a Display Program.

From a user's point of view, there will be a software switch to control between the two modes of Normal Operation and Logging Operation.

The method discussed below needs the following resources: 1. Attachment Processor (AP) logging counters - 1024 bytes AP Memory (system memory) for 256 32-bit counter is required; 2. AP decoding RAM area - 512 bytes AP Memory (system memory), for storing the 256 16-bit registers for Display Processor (DP) microcode decoding in the normal operation; 3. some DP microcode storage space at fixed location; 4. several DP scratch pad RAM registers; 5. an AP-to-DP request code; 6. a normal/logging switch register in AP-DP Communication Area; 7. a pointer in AP-DP Communication Area contains the address of AP logging counter area; 8. a pointer in AP-DP Communication Area contains the address of AP decoding RAM area. Graphics Order Decoding

In decoding, 256 scratch pad RAM registers are used to contain the addresses of the subroutine handling the loading of a particular graphics order.

There is a piece of hardware checking the first byte of each 16- bit word read in from the system memory. If it detects Hex 2A, 2E, 2C, 28, then it sets a flag, which can be tested by microcode. (Sometimes 2Axx can be part of data word).

Take the decoding for a graphics order 2Axx as an example: (See Fig. 1). 1. The word '2Axx' is read into a register GR/, it is also saved in a scratch RAM register 'dir'; 2. After the hardware detects the '2A'; 3. It then masks the higher byte with 0, and puts the result back in GR/. 4. The addresses of the subroutines to execute graphics orders are contained in 256 consecutive scratch pad RAM registers.

The beginning address is X'800', which can be addressed by a strobe "load rampagel". 5. Use GR/ as an index to jump to the subroutine handling 2Axx with address contained in the scratch RAM register X'800' GR/. Graphics Order Decoding Logging Mode

This section covers the DP operation in the Logging Mode.

The logic sequence in the decoding mode is: 1.detect opcode; 2.branch to a Logging subroutine; 3.resume the normal decoding procedure.

During the operation, the Logging Subroutine is in a fixed location with the beginning address "logaddr".

The 256 decoding RAM in the last section will be saved in the AP decoding RAM area; and the 256 DP decoding registers will be loaded with the same

1

Page 2 of 5

address "logaddr". (See the next section on AP-DP.) 1. During the decoding phase in the Logging mode, the Logging Subroutine is executed first:

The following shares in the same code as the normal operation. a. The word '2Axx' is read into a register GR/, it is also saved in a scratch RAM register 'dir';
b. After the hardware detects the '2A'; c. It then masks the hi...