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Breakpoint Bit Technique for an Address Compare Function

IP.com Disclosure Number: IPCOM000035639D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Millas, RJ: AUTHOR [+3]

Abstract

This article describes a technique which provides a breakpoint function in a processor without the use of extra comparison logic and with minimal delay.

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Breakpoint Bit Technique for an Address Compare Function

This article describes a technique which provides a breakpoint function in a processor without the use of extra comparison logic and with minimal delay.

A circuit designed for tracing the address flow of a processor (microprocessor, digital signal processor, etc.) must make an address comparison to begin or stop a trace. To do this a trigger address or breakpoint is usually written to a breakpoint register. This register is periodically compared to the address on the processor's address bus. If a match is detected by a comparator circuit, a breakpoint is found and the address trace logic can begin or halt a trace. This same technique is typically used in stop-on-address circuits to halt a processor at a given address.

The logic required to perform a breakpoint detection typically consists of a breakpoint register and a comparator as shown in Fig. 1. The size of the breakpoint register and comparator depends on the size of the address bus being monitored. For example, on a 14-bit address bus, the register and comparator could easily take up over 100 logic gates if implemented in very large-scale integration (VLSI).

The faster the processor, the faster the comparison must be made. This is extremely important when monitoring very fast processors such as digital signal processors.

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Fig. 2 illustrates the technique of this disclosure wherein a 14- bit address bus of a digital signal processor (DSP...