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Redundancy and Logic-Ec Scheme for Passive Superchip

IP.com Disclosure Number: IPCOM000035652D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+4]

Abstract

A method is described which allows increasing the process yield of silicon carriers by using a system of redundant wires.

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Redundancy and Logic-Ec Scheme for Passive Superchip

A method is described which allows increasing the process yield of silicon carriers by using a system of redundant wires.

Strong limitations still existing with regard to the size of silicon carriers are overcome by increasing the process yield which is limited mainly by defect mechanisms, such as metal shorts, metal opens and interlevel shorts.

The proposed method may also be used to correct logic design errors. For this purpose, the wiring connections between the chips are changed, which avoids the cost-intensive step of changing the logic chips at an early stage.

The figure shows schematically how signal lines are replaced by redundant lines.

The substrate consists of three metallization layers M1, M2 and M3, M1 being used only for power wiring and M2 and M3 for signal wiring. For clarity, the figure shows a 2-point bus concept with three representative bus connections A, B and C as well as three representative redundant lines R1, R2 and R3 arranged parallel thereto. The signal bus and the RED/EC (Reduncancy/Engineering Change) bus is wired mainly on M3. The dashed lines represent an M2 wiring connecting the RED/EC bus to M2 pads located directly below the M3 signal line pads 1 to 6.

Opens and shorts occurring in one or several of the signal lines are repaired as follows.

After a wafer test has located an open in, say, signal line A, an additional process step connects the redundant line, say, R1, to defecti...