Browse Prior Art Database

Asymmetric CMOS Logic Gates

IP.com Disclosure Number: IPCOM000035660D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Loehlein, WD: AUTHOR

Abstract

By using asymmetric logic gates in a logic design system, the critical path is considerably improved.

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Asymmetric CMOS Logic Gates

By using asymmetric logic gates in a logic design system, the critical path is considerably improved.

Conventionally, logic books in CMOS technology have fixed device sizes and are optimized to have symmetrical turn-on and turn-off times. Fast turn-on and turn-off delays are provided so that the signals along the critical path coincide with each other at the data link, the respec tive adequate version employed depending on the scope of the logic book.

An embodiment using two versions - fast turn-on and fast turn-off - is described which improves the delay times for each logic function.

(Image Omitted)

Fig. 1 is a circuit diagram of a three-way AND inverter with standard devices. By changing the device width over that of state-of-the-art devices (Table 1), the turn- on and turn-off times are improved, as shown in Table 2. Fig. 2 shows different logic books, the hatched and blank areas representing the width of P and N devices, respectively. From left to right, a standard book made up of four symmetric cells, fast turn-on and turn-off books comprising three and two cells, respectively, and a three-cell standard book are shown. The N and P devices of each basic cell are identically dimensioned, say, 89.6 m x 13.8 m, so that the books can be placed in any order and are fully compatible.

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