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Prediction of Shift Left Single and Shift Left Double Overflow Condition

IP.com Disclosure Number: IPCOM000035677D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 95K

Publishing Venue

IBM

Related People

Huffman, AE: AUTHOR [+2]

Abstract

In IBM System/370 and System/370 Extended Architecture there is an overflow condition code for the instructions Shift Left Single (SLA) and Shift Left Double (SLDA). The SLA and SLDA instructions are arithmetic shifts which means the sign bit (the high-order bit of data) does not participate in the shift. The overflow condition code is defined as the detection of any bits being shifted out that are different from the sign bit. This condition is easily detected if the shift is performed with shift registers. However, most processors perform this shift in a single clock cycle because it is faster.

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Prediction of Shift Left Single and Shift Left Double Overflow Condition

In IBM System/370 and System/370 Extended Architecture there is an overflow condition code for the instructions Shift Left Single (SLA) and Shift Left Double (SLDA). The SLA and SLDA instructions are arithmetic shifts which means the sign bit (the high-order bit of data) does not participate in the shift. The overflow condition code is defined as the detection of any bits being shifted out that are different from the sign bit. This condition is easily detected if the shift is performed with shift registers. However, most processors perform this shift in a single clock cycle because it is faster. Therefore, to detect this condition in most processors, circuitry is required to either duplicate the shifter to maintain the bits shifted out instead of the shift result, or to compare the number of O's and l's in the shifter output with the number of O's and l's in the shifter inputs. In both cases the condition is not detected until some time after the shift is completed. A logic design that predicts the overflow condition code of both the SLA and SLDA instructions in fewer circuits than current designs and in parallel with the shift itself is described in the following.

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The overflow predictor uses as inputs a six-bit shift amount and 64 bits of data (Fig. 1). The six-bit shift amount is the low-order six bits of the result achieved by adding base register Bl to the displacement amount Dl of the SLA or SLDA instruction. It is assumed that this addition has been completed before the predictor. For the SLA instruction, the high-order 32 bits of the input data are the contents of the Rl register specified in the instruction and the low-order 32 bits are zeroes. For the SLDA instruction, the high-order 32 bits of the input data are also the contents of the Rl register, but the low-order 32 bits are the contents of the Rl + 1 register (the odd register of the even-odd register pair). This data also feeds the shifter inputs.

The problem of determining overflow consists of four separate cases. The first case is determining if any l's are shifted out when the sign bit (the high-order bit of the input data) is 0 for SLA (Fig. 2). The second case is determining if any O's are shifted out when the sign bit is 1 for SLA (Fig. 3). There are also two more similar cases for the SLDA instruction (Figs. 4 and 5). These four cases are combined into one for this overflow predictor (Fig. 6). This is achieved by conditionally inverting the input data when the sign bit is 1 (this function is performed by Exclusive-OR logic gates). Therefore, only l's being shifted out need to be detected, not O's. This means bit 0 is always a zero after the conditional inversion and is not needed in the circuits that follow the inversion. The SLA instruction is made to look like the SLDA instruction by requiring the low-order 32

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bits of input data to be zeroes (accomplish...