Browse Prior Art Database

Phase-Locked Loop With Programmable Phase Offset

IP.com Disclosure Number: IPCOM000035682D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Coburn, RL: AUTHOR [+2]

Abstract

Disclosed is an implementation of a Phase-Locked Loop (PLL) with incremental taps for adjusting phase offset.

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Phase-Locked Loop With Programmable Phase Offset

Disclosed is an implementation of a Phase-Locked Loop (PLL) with incremental taps for adjusting phase offset.

Phase-Locked Loops are widely used to recover timing signals in all types of circuits. These PLLs are usually integrated which greatly reduces their cost. Unfortunately, the performance of the PLL is directly dependent upon process variations. These variations affect the closed loop parameters and deviations from the ideal PLL operation. Variations in the loop parameters can be controlled through careful design practices. The control of deviations is more difficult. For example, static phase offset is usually inherent in the PLL design; phase offset is the phase difference between the ideal recovered clock timing and the actual recovered clock signal. Phase offset is usually process dependent.

A block diagram of the adjustable phase offset PLL is shown in Fig. 1. The adjustable phase offset PLL includes VCO 10 formed from a plurality of series- connected delay blocks 1 .... n. The delay blocks (detail of which is shown in Fig.
2) are configured as a ring oscillator. By digitally selecting a given tap, any PLL static phase offset can be negated within the resolution of the delay blocks. As various taps of the VCO are selected via the multiplexer, many phase relationships can be set up with the reference input.

What makes this possible is a ring oscillator built of the inverter stages shown also in Fig. 1. Th...