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Clock Phase Compensator

IP.com Disclosure Number: IPCOM000035684D
Original Publication Date: 1989-Jul-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Ono, H: AUTHOR [+3]

Abstract

A clock phase compensator is described which is suitable for a clock signal generator of MHz range to be synchronous to external trigger pulse. Conventionally, an externally cleared divider and a higher frequency base clock are used to generate a synchronous clock. For example, when 5 nsec of phase accuracy is required for a 10 MHz clock, a 200 MHz base clock and a 1/20 ECL (Emitter Coupled Logic) divider circuit must be used. This clock phase compensator achieves the same function by using a multi-tap delay module and a TTL circuit under lower frequency base clock.

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Clock Phase Compensator

A clock phase compensator is described which is suitable for a clock signal generator of MHz range to be synchronous to external trigger pulse. Conventionally, an externally cleared divider and a higher frequency base clock are used to generate a synchronous clock. For example, when 5 nsec of phase accuracy is required for a 10 MHz clock, a 200 MHz base clock and a 1/20 ECL (Emitter Coupled Logic) divider circuit must be used. This clock phase compensator achieves the same function by using a multi-tap delay module and a TTL circuit under lower frequency base clock.

Fig. 1 is a block diagram showing one example of this clock phase compensator. In Fig. 1, a base clock is loaded to a delay line input.

(Image Omitted)

When the sync pulse is triggered, the latch detects the delay output which shows the phase status of the base clock and sends it to a ROS (Read-Only Storage). Delay line selection map is written in the ROS. One of the delay lines is picked up by a selector according to a ROS output code. Thus, a selected signal is synchronous to the trigger pulse. A divider counts down the synchronized base clock, and a clear pulse has the same timing with the trigger pulse. The divider output signal is finally synchronous to the external trigger.

The number of taps is determined by the relation of base clock frequency, tap delay time and the output clock specification described in Equations 1 and 2. TN = 1/(BCF * DT) + 2 (Taps) Equation 1 OCP = DT * OCF * 360 (degrees)

Equation 2 where TN = Number of taps of the delay line (Taps) BCF = Base clock frequency (Hz) DT = Delay time of each tap (sec.) PCP = Output clock phase accuracy (degree) OCF = Output clock frequency (Hz)

Equation...