Browse Prior Art Database

TEST Bus Architecture

IP.com Disclosure Number: IPCOM000035697D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 124K

Publishing Venue

IBM

Related People

Bardell, PH: AUTHOR [+4]

Abstract

Disclosed is an implementation of the test access port associated with a defined four-wire test bus, the whole designed for the support of boundary scan testing and the control of other built-in design-for- testability features. The implementation is compatible with Level- Sensitive Scan Design (LSSD) and with the testability bus standard proposed by the Joint Test Action Group (JTAG). (Image Omitted)

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TEST Bus Architecture

Disclosed is an implementation of the test access port associated with a defined four-wire test bus, the whole designed for the support of boundary scan testing and the control of other built-in design-for- testability features. The implementation is compatible with Level- Sensitive Scan Design (LSSD) and with the testability bus standard proposed by the Joint Test Action Group (JTAG).

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The Test Access Port (TAP) on the application (a VLSI chip, a multichip module or card) is controlled by a 4-wire bus that transfers bit serial data between a master bus controller and one or more TAPs. The 4-wire bus signal types are: TCK A free-running single phase Test Clock with nominal 50% duty cycle. All control and data transfer operations on the bus are synchronized with TCK. Input values are captured on the rise of TCK and data outputs change on the fall of TCK. Using TCK to satisfy the master/slave clocking requirements of LSSD requires that either a) two chopped clocks are generated from the leading and trailing edges of TCK or b) two LSSD clocks are provided and synchronized correctly with TCK. The timing of the LSSD clocks relative to TCK is shown in Fig. 1. The leading edges of the LSSD clocks are not critical, but the trailing edges must occur well before the next transition of TCK. A standard clock- chopper circuit can be used to produce C1 and C2 from TCK. In the following the free-running C1 and C2 clocks shown in Fig. 1 are assumed available internal to the Test Access Port. Input values to the TAP are captured on C1 and TAP output values change on C2.

TDI A unidirectional serial Test Data Input line used by the bus controller to send instructions to the TAP instruction register or data to the application registers. The bus controller shall change the data bit on an active C2 clock and the data shall be valid to the TAP on the succeeding C1 clock.

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TDO A unidirectional serial Test Data Output line used to send instruction register or application register contents from the TAP to the bus controller. The TAP shall change the TDO data bit on an active C2 clock and it shall be valid on the succeeding C1 clock to the bus controller. The TDO output shall be tri-stated when not active to support a hardwired OR function. The TAP shall control tri- state operations on the TDO driver.

TMS A unidirectional serial Test Mode Select line to the TAP used to establish the type of operation being performed. TMS signals are decoded by a state machine in the TAP to control the other parts of the port, the application data registers, or those test facilities built into the application.

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The Test Access Port consists of a state machine and a scannable instruction register. The state machine has 16 states and it takes 4 bits to represent them. Fig. 2 shows the flowchart of the state machine and the state

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assignments chosen. In Fig. 2, IR means instruction register and DR...