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Browse Prior Art Database

Short-Channel Field-Effect Transistor

IP.com Disclosure Number: IPCOM000035718D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Brodsky, MH: AUTHOR [+5]

Abstract

A short-channel field-effect transistor is fabricated using a bevelled four-layer alternate metal and insulator sandwich with the source and drain, the alternate metal layers and the gate positioned on the bevel. The structure is shown in the figure.

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Short-Channel Field-Effect Transistor

A short-channel field-effect transistor is fabricated using a bevelled four-layer alternate metal and insulator sandwich with the source and drain, the alternate metal layers and the gate positioned on the bevel. The structure is shown in the figure.

The structure is based on a multilayer edge formed from a four film sandwich consisting of metal, insulator, metal, insulator. The metals are the source and drain for the device. The edge is covered with channel material, gate insulation, and gate metal layers.

The initial four film sandwich (M1, I1, M2, I2) includes the source (M1) and drain (M2) as well as insulation (I1) to isolate the electrically active layers from each other. The edge is formed by liftoff or by etching. By an appropriate choice of metals, insulators, and etch gases, a sloping edge with a well-controlled angle can be formed.

Following an appropriate preclean and anneal, if necessary, the semiconductor channel (SC), gate insulation (I3), and gate metal (M3) are deposited. These layers could be deposited through a single mask, even in a single deposition system if desired. The channel material can be amorphous or crystalline. The channel length is determined by the I1 thickness, a parameter which can be well controlled. Both channel and gate insulator thickness can also be precisely controlled. There is some parasitic capacitance due to overlap of gate and drain. It can be reduced by using thin M2 and/or thick...