Browse Prior Art Database

Set and Reset Per Mask Functions

IP.com Disclosure Number: IPCOM000035725D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Concha, FF: AUTHOR [+4]

Abstract

This article describes a technique for use in a central processing unit (CPU) wherein controls are provided on the interchip busses and a microcommand to execute a set or reset (S/R) per the parameter field of an instruction.

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Set and Reset Per Mask Functions

This article describes a technique for use in a central processing unit (CPU) wherein controls are provided on the interchip busses and a microcommand to execute a set or reset (S/R) per the parameter field of an instruction.

In some CPUs, enable and disable instructions provide for setting (enable) or resetting (disable) system wide controls as prescribed in the parameter field of the instruction. Microcoded bit testing of the parameter field and then executing the proper dedicated microinstruction becomes too time consuming particularly when multiple parameters are specified.

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Referring to Fig. 1 which is a block diagram of the system logic, the set and reset per mask function provides for simultaneous set or reset of these system wide controls using the following key controls. A control (next B source I-buffer word) is generated during the cycle in which the CPU instruction (enable or disable) is being decoded. During the following cycle which is the first microcycle of the enable or disable instruction, the next B source I-buffer word control is executed to put the parameter field on the processor B-bus. During the second cycle, the mask from the B-bus has been propagated through the arithmetic logic unit (ALU) and broadcasted on the ALU bus to all parts of the system responsible for executing from the mask. Also during the second cycle, a set per mask (if the instruction is enable) or reset per mask (if the ins...