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Switched Biphase Digital Phase-Locked Loop

IP.com Disclosure Number: IPCOM000035740D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Garcia, C: AUTHOR [+3]

Abstract

Disclosed is a high-performance new digital phase-locked loop (PLL) and specifically, a digital PLL which allows, with a given clock rate, doubling the performance of the conventional digital PLLs.

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Switched Biphase Digital Phase-Locked Loop

Disclosed is a high-performance new digital phase-locked loop (PLL) and specifically, a digital PLL which allows, with a given clock rate, doubling the performance of the conventional digital PLLs.

The conventional digital PLL is coupled to a clock signal which provides a reference operating frequency and is typically divided to the exact operating frequency of the loop. In addition to the frequency divider, the conventional digital PLL circuit comprises a phase comparator and a phase compensation network. In operation, the divided operating frequency is coupled to the phase comparator, which compares the phase of the divided operating frequency with the phase of the received data signal. The phase comparator instructs the phase compensation circuit to adjust the phase of the divided clock by advancing or delaying the phase of the divided clock signal. Thus, the minimum jitter provided by such a circuit corresponds to one period of the clock signal.

To improve minimum jitter and consequently increase the highest receivable data signal frequency supported by the conventional digital PLL, it would normally be necessary to increase the clock signal frequency, provided indeed, that the digital PLL logic can support it.

The present alternative, called 'switched biphase' digital PLL, solves this problem by switching the phase of the clock signal coupled to the digital PLL by its reverse companion clock having the same frequenc...