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Simconvert - an Automated Method for VLSI Simulation to Test Vector Conversion Using Test Program Information

IP.com Disclosure Number: IPCOM000035743D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 88K

Publishing Venue

IBM

Related People

Becker, DO: AUTHOR

Abstract

This article describes a method that automatically converts very large- scale integration (VLSI) design system simulation files to VLSI test system vectors using timing and sampling information (the AC specification) found in the test program information. Input files required by SimConvert: Device simulation file - a file containing the state of each pin of the device. This file is obtained from VSLI device simulator which outputs the states and the time at which they occur in ascending order. State or Cycle file - a file containing a list of states or cycles of the device in the sequence that they occur in the simulation file. Output files created by SimConvert: Vector file - VSLI test vector for the target VLSI test system. Error file - a file containing problems and diagnostic information found during the vector conversion.

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Simconvert - an Automated Method for VLSI Simulation to Test Vector Conversion Using Test Program Information

This article describes a method that automatically converts very large- scale integration (VLSI) design system simulation files to VLSI test system vectors using timing and sampling information (the AC specification) found in the test program information. Input files required by SimConvert: Device simulation file - a file containing the state of each pin of the device. This file is obtained from VSLI device simulator which outputs the states and the time at which they occur in ascending order. State or Cycle file - a file containing a list of states or cycles of the device in the sequence that they occur in the simulation file. Output files created by SimConvert: Vector file - VSLI test vector for the target VLSI test system. Error file - a file containing problems and diagnostic information found during the vector conversion.

In addition to the named input and output files, SimConvert requires that an AC test specification be defined and is accessable on the VLSI test system. The AC specification consists of a table or list of states or cycles that are possible for the device. Each cycle is given a name such as MemoryReadCycle, IOWriteCycle, WaitCycle, etc. Each cycle in the cycle table lists the waveforms that are assigned to each pin of the device. Each waveform is defined in a waveform table that defines the change to the logic state or edge of the pin and the time at which the change occurs. Typical edge types include DriveHigh, StrobeLow, StrobeZ, etc. The time of the edge is usually referenced as a variable that is defined in an AC data sheet. An example is illustrated below.

Cycle Table: ReadCycle, Pinx, ReadWaveform

WriteCycle, Pinx, WriteWaveform

Waveform Table:

ReadWaveform, Edge1, StrobeOff, t1min

Edge2, StrobeData, t1max

Edge3, StrobeOff, t1max + t2min

Edge4, StrobeZ, t1max + t2max

WriteWaveform, Edge1, StrobeOff, t3min

Edge2, DriveData, t3max

Edge3, DriveOff, WriteCyclePeriod+4max

Edge4, StrobeZ, WriteCyclePeriod+4min

AC Data Sheet:

ReadCyclePeriod = 100ns WriteCyclePeriod = 150ns

t1min = 60ns t1max = 65ns t3min = 30ns t3max = 35ns

t2min = 20ns t2max = 30ns t4min = 20ns t4max = 25ns

The method disclosed herein is illustrated in the flow charts of Figs. 1A through 1E. Following is a description of each numbered block of the flowcharts:

(Image Omitted)

1.All variables are initialized. Primary variables used by SimConvert are:

1

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A queue of pending edges (or events) for each pin. Edges: define intended changes to the driving or strobing of a pin. SimConvert handles the following type of edges: DriveHigh, DriveLow, DriveData, DriveComplement, DriveOff, StrobeHigh, StrobeLow, StrobeData, StrobeComplement, StrobeZ, StrobeOff, EdgeStrobeHigh, EdgeStrobeLow, EdgeStrobeData, EdgeStrobe- Complement, EdgeStrobeLatch. These edges are abbreviated respectively as follows: DH, DL, DD, DC, DO, SH, SL, SD, SC, SZ,...