Browse Prior Art Database

Programmable Delay Line for Image Analysis

IP.com Disclosure Number: IPCOM000035745D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Picunko, T: AUTHOR [+2]

Abstract

Disclosed is a circuit which permits the selection of data byte positions in a stream of sequential video pixel data where such positions are separated by known intervals. The data in these positions are then presented simultaneously, as in the manner of a tapped delay line, for further processing in an image analysis algorithm.

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Programmable Delay Line for Image Analysis

Disclosed is a circuit which permits the selection of data byte positions in a stream of sequential video pixel data where such positions are separated by known intervals. The data in these positions are then presented simultaneously, as in the manner of a tapped delay line, for further processing in an image analysis algorithm.

Fig. 1 represents an example of the spatial relationship on a given image of the pixels which are to be separated out of the video data stream. Each square in the figure represents a pixel on the image and the three cross-shaped groups are the pixels of interest at any instant of time. The groups move across the image as the scanning process occurs. For convenience, the groups are identified as left, center and right with each group further divided into center, north, south, east and west. In this case, the left and right groups are always equally separated from the center group by a selectable known interval R. The maximum number of pixels in one horizontal scan of the image is called W. It can be seen by inspection that the center north (CN) pixel is separated from the right north pixel (RN) by an interval R and that the RN pixel is separated from the left west pixel (LW) by an interval W-2R.

Separation of the data bytes representing the desired pixels may be performed using conventional commercial first-in, first-out (FIFO) memories. However, conventional FIFO devices exhibit a condition known as "bubble- through" which prevents their use at the high clock rates used in video applications.

(Image Omitted)

This condition is avoided by the use of conventional random-access memory (RAM) devices arranged so as to permit simultaneous reading and writing, as shown in Figs. 2A and 2B. Clocking, counting and switching means are not shown for clarity. The switch contacts shown in Figs. 2A and 2B represent gated logic devices. Simultaneous reading and writing is accomplished by using two groups of RAM memory such that new data is being written to the first group while previously written data is being read fr...