Browse Prior Art Database

Timing Verification of Algorithmically Grown Macros

IP.com Disclosure Number: IPCOM000035787D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 30K

Publishing Venue

IBM

Related People

Bond, CS: AUTHOR [+4]

Abstract

A method is shown for calculating accurate and complete delays for algorithmically grown macros, and the application of these delays to perform critical timing checks for a macro within a chip environment during timing analysis.

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Page 1 of 4

Timing Verification of Algorithmically Grown Macros

A method is shown for calculating accurate and complete delays for algorithmically grown macros, and the application of these delays to perform critical timing checks for a macro within a chip environment during timing analysis.

A stand alone analysis tool developed for FET technologies called Early Timing Estimator (ETE) is utilized to provide the logic/chip designer with timing information at various stages throughout the design process. Logic is supplied to ETE through a logic description language and delays for a circuit are described through technology data by relating an input pin to an output pin. Possible timing checks include data setup/hold time, clock pulse widths and clock separation. ETE calculates rising and falling delays and output transition times from the following standard FET equations: Td = (K1 + K2*CL)*Tx + K3*CL**2 + K4*CL + K5

where:

Td = delay value (TPLH, TPHL, TRO, TFO)

K1,....,K5 = delay equation constants in ETE

rules.

CL = net loading capacitance (in pf).

Tx = input rise or fall time.

and

TPLH = time to propagate from low to high as

output.

TPHL = time to propagate from high to low at

output.

TRO = rising output transition.

TFO = falling output transition.

Delays through an algorithmically grown CMOS macro consist of internal bulk delays (unique personality and macro size, e.g., number of product terms for a programmable logic array - PLA) and external delays (sensitivity to global conditions of input pin transition times and output pin loading capacitance) of the macros. Delay can be calculated by the standard FET delay equation shown.

To accurately analyze growable macro performance within the chip environment, both internal and external delay components must be available during timing analysis. ETE has access to the external components and the equation describing their effects through the technology data, but has no knowledge of the macro personality and size. To account for this, the internal bulk delay component is passed to ETE as a fixed format file that is created at the time of macro generation by the macro generation tool. This file contains macro "adders" which are rising/falling delays assigned to macro input pins and output pins. The macro adder delays are then applied to the overall macro delay during chip delay calculations. The total macro delay computed by ETE for a PLA, for a random-access memory (RAM) or a read-only store (ROS) is the standard FET delay equation plus macro adders.

1

Page 2 of 4

Critical timing requirements are specified in the technology data for each generic macro to test if minimum clock width, and minimum control/data signal setup times are met. The macro adder delays are applied during timing analysis to incorporate the actual timing requirements based on the macro configuration, for example, the minimum dat...