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Bifet Variable Gain Amplifier With Maximized Control Voltage Range

IP.com Disclosure Number: IPCOM000035788D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Richetta, RA: AUTHOR [+2]

Abstract

This circuit is used in the read data path of a direct access disk drive. The analog disk signal from the head pre-amp output must be normalized to a constant amplitude, independent of disk signal amplitude variations. A Variable Gain Amplifier (VGA) in a feedback loop is used to perform the amplitude normalization. The variable gain is obtained by modulating the gate to source voltage of an NFET and, therefore, its channel resistance. The NFET device is connected between the emitters of two NPN transistors. Because of the other circuit design tradeoffs, the source and drain voltages of the NFET, at normal gains, vary statistically and with temperature. An external feedback loop around the VGA compares the output AC level against the desired level and generates an error voltage.

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Bifet Variable Gain Amplifier With Maximized Control Voltage Range

This circuit is used in the read data path of a direct access disk drive. The analog disk signal from the head pre-amp output must be normalized to a constant amplitude, independent of disk signal amplitude variations. A Variable Gain Amplifier (VGA) in a feedback loop is used to perform the amplitude normalization. The variable gain is obtained by modulating the gate to source voltage of an NFET and, therefore, its channel resistance. The NFET device is connected between the emitters of two NPN transistors. Because of the other circuit design tradeoffs, the source and drain voltages of the NFET, at normal gains, vary statistically and with temperature. An external feedback loop around the VGA compares the output AC level against the desired level and generates an error voltage. The error voltage is positive to increase gain and negative to decrease gain. This error voltage is usually generated with respect to an external reference voltage, and must therefore be translated to the center of the range of the gain-changing element. It is desirable to maximize the control voltage range which changes the gain from max to min in order to maximize noise immunity. To do this, the control voltage translation circuit must track the temperature, voltage, and statistical variations of the nonlinear gain changing element, in this case an NFET device.

A VGA with a novel control voltage translation circuit is described which maximizes the VGA control voltage range.

The figure shows a schematic of the VGA circuit described herein. The differential, variable, input signal arrives AC coupled to connector pins FB0 and FD0. Connector FV0 is a reference voltage at 1/2 the minimum power supply voltage. NFETs T3 and T4 are switches that allow the input AC coupling to be selectively disabled. T5 and T6 invert the HOLD signal from connector AH0 to the gates of T3 and T4. Resistors R1 and R2 form the resistive termination of AC high-pass coupling. The differential input signal is now at the bases of Q3 and Q4 which forms the input of the variable gain stage. Q9, R9 and Q10, R10 are the current sources for the variable gain stage. They are biased from a bias reference voltage at connector FA0. T12's channel resistance is the emitter resistance term of the variable gain stage. The gate of T12 receives the level translated and centered control voltage. Q23 and Q24 form a cascode stage to Q3 and Q4 for boosted frequency response. R5 and R6 are the collector resistors of the variable gain stage. T23 is an NFET current source biased from a reference voltage at connector AN0. T23's drain current is mirrored by T22 and T9 and conducted through diodes Q26 and Q27 to bias the cascode stage and the collector resistors. Q22 and Q21 are emitter followers that translate from the output of the first variable gain stage to the second fixed gain stage. T15 and T17 are the emitter follower current sources.

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