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Auto-Refresh Timer for Dynamic Random-Access Memory

IP.com Disclosure Number: IPCOM000035795D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Ohsaki, K: AUTHOR [+2]

Abstract

An auto-refresh timer for a Dynamic Random-Access Memory (DRAM) is presented, which can track data retention time of memory cells which may vary with process condition and operating condition of the DRAM.

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Auto-Refresh Timer for Dynamic Random-Access Memory

An auto-refresh timer for a Dynamic Random-Access Memory (DRAM) is presented, which can track data retention time of memory cells which may vary with process condition and operating condition of the DRAM.

In the figure, C1-C4 are capacitors formed on the silicon substrate side by side in the same mask level as the memory cells. R1-R4 represent parasitic resistances which act as leakage paths of the capacitors C1-C4. R12, R23 and R34 also represent parasitic resistances which act as leakage paths between adjacent capacitors. G is a differential amplifier which has a predetermined offset voltage, Voffset. Output signal Vout from the differential amplifier G is connected to a RAS (Row Address Strobe) only refresh circuit.

At the beginning of each refresh cycle, the capacitors C1-C4 are charged by clock d to the following values. V1=Vdd, V2=Va, V3=Vb and V4=0 where 0 < Va < Vb < Vdd With the capacitors C1-C4 charged, the output Vout is low.

After the clock d goes low, the capacitor voltages V2 and V3 begin to vary. That is, the charge stored in C2 leaks through R2, while the charge in C1 and C3 leaks through R12 and R23 to C2 to slow down its decay. The charge in C3 also leaks through R3 and R34. Then the voltage difference between V2 and V3 becomes smaller and finally falls within the offset voltage of the differential amplifier G. V2-V3 < Voffset

When this occurs, the output Vout goes from low to high and activate...