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Floating Point Processing Element Microcode Matrix Chart

IP.com Disclosure Number: IPCOM000035796D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Grant, MR: AUTHOR [+3]

Abstract

This article describes a floating point processing element (FPPE) microcode matrix chart, hereinafter referred to as the matrix chart, a tool which aids the FPPE microprogram developer. FPPE microprogram source code mnemonics, entered by the microprogrammer, are translated by a computer program, the FPPE micro-assembler, to the actual object code which controls the processor. This source code, as is often the case with microprogram source code, is cryptic and does not represent the operations of the microprogram well.

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Floating Point Processing Element Microcode Matrix Chart

This article describes a floating point processing element (FPPE) microcode matrix chart, hereinafter referred to as the matrix chart, a tool which aids the FPPE microprogram developer. FPPE microprogram source code mnemonics, entered by the microprogrammer, are translated by a computer program, the FPPE micro-assembler, to the actual object code which controls the processor. This source code, as is often the case with microprogram source code, is cryptic and does not represent the operations of the microprogram well.

The fundamental function of the matrix chart is to translate microprogram source into a standard format capable of being read and reviewed by other microprogrammers and microprogram users. In the past, handwritten matrix charts were a standard part of the documentation. Matrix charts were only available to enable microprogram maintenance. The tedious and error-prone process of manually generating the matrix chart was too costly in time and microprogrammer effort to allow it to be done more than once -- at the completion of the coding effort.

The FPPE is a parallel pipelined processor. On every clock cycle, one 128- bit microinstruction is fetched from storage and that instruction's controls are presented to the data flow components. The FPPE data flow is parallel as it is based on two parallel sets multiplier/accumulator/ALU pipes. The FPPE microinstruction generally controls these parallel pipes in lockstep, but some autonomous control is required for each pipe for the effective use of resources (e.g., data buses) which are shared by both pipes. The FPPE data flow is pipelined, as on any given instruction, several operations may be initiated, but no operation is completed in one cycle. Microprogram operations span several instr...