Browse Prior Art Database

Multiplexing Register With Pulsed Feedback and Feedback Refresh

IP.com Disclosure Number: IPCOM000035799D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Berger, RW: AUTHOR

Abstract

In prior-art multiplexing registers, a DC design failure occurs due to the inability of these circuits to sink the current sourced by several multiplexing registers using standard feedback techniques. This article describes a multiplexing register that overcomes the limitations of the prior art by utilizing pulsed feedback and feedback refresh techniques.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 2

Multiplexing Register With Pulsed Feedback and Feedback Refresh

In prior-art multiplexing registers, a DC design failure occurs due to the inability of these circuits to sink the current sourced by several multiplexing registers using standard feedback techniques. This article describes a multiplexing register that overcomes the limitations of the prior art by utilizing pulsed feedback and feedback refresh techniques.

In the figure, a multiplexing register designed in accordance with the invention is shown. A pair of P feedback devices 3 and 5 are connected in series. Node "A" will be pulled up to a full logic "1" during a short "pulse" period in which both node "B" and node "C" are at "0." After a short delay, node C switches to a "1" shutting off P device 5. When node A needs to be pulled to a "0," there is no connection of A to the VDD supply. Node B goes to a "1," shutting off P device 3 before P device 5 turns back on.

The feedback pulse duration is the delay of the inverter between nodes B and C, which is a function of the inverter device sizes, P device 7 and N device 8, and the capacitance of node C. To increase the pulse width, P device 7 should be long and narrow. The rate at which node A is pulled up is a function of the "on resistance" of feedback devices 3 and 5, which should be short and wide.

There is a problem with this feedback pulse approach. Because the pulse is generated only by a "0" --> "1" transition at node A, the full "1" will leak away (...