Browse Prior Art Database

Mixed Memory CARD SELECTOR

IP.com Disclosure Number: IPCOM000035804D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Grosbach, LE: AUTHOR

Abstract

The CARD SELECTOR is defined to allow mixing of Main Storage cards that us either 1-Mbit or 4-Mbit Dynamic Random-Access Memories (DRAMs).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 4

Mixed Memory CARD SELECTOR

The CARD SELECTOR is defined to allow mixing of Main Storage cards that us either 1-Mbit or 4-Mbit Dynamic Random-Access Memories (DRAMs).

The IBM System/38 Computer uses a Primary Directory table to store information about each page in memory. One page contains 512 bytes. Each Primary Directory table entry uses 32 bytes of memory.

The current IBM System/38 allocates pages to all memory cards as if all of the memory cards are the same size. This allocates very large blocks of unusable pages when memory cards of very different sizes are installed in the same system. Every unusable page in memory counts in the total of allocated memory pages.

The CARD SELECTOR accomplishes the following:

Mixing of different sizes of memory cards.

Always able to create the smallest Primary Directory.

Memory card address selection is controlled by

Diagnostic Horizontal Microcode (DHMC) (microcode

controlling diagnostics).

Logical Map of up to four 1-Mbit DRAM memory cards into

one 4 Mbit DRAM memory card.

Allocates Main Store by memory blocks not memory size.

(Image Omitted)

The current design of the IBM System/38 CPU allows an HMC (horizontal microcode) controlled logical allocation of up to 6 identical memory cards. This SELECTOR is an extension of this idea to include mixing similar memory cards using 1 Mbit and 4 Mbit DRAMs.

The SELECTOR allows DHMC to allocate memory according to number of array blocks. The hardware used for this function is an Address Formatter, a Memory Configuration Register (MCR), a Slot Register, and Main Store (MS) Vital Product Data (VPD) (all subsequently defined herein).

The memory cards are divided into array blocks that contain 2 MBytes of memory using a 1-Mbit DRAM and 8 MBytes of memory using a 4- MBit DRAM. Fig. 1 shows a typical memory card. Each Main Store card VPD contains the size, and type of the MS card.

The MCR is a table of physical card IDs. The MCR has two locations for each physical card slot. One location is for a card with 4-Mbit

(Image Omitted)

DRAMs; the other location is for a card with 1-Mbit DRAMs. Another register is the SLOT register. It is a register that contains one CARD ID. The card ID in the

1

Page 2 of 4

SLOT register is the address range where up to four 1-Mbit DRAM Main St...