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Easy Biased Exponent Handling Via 2's Complement Arithmetic

IP.com Disclosure Number: IPCOM000035807D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 159K

Publishing Venue

IBM

Related People

Brown, JD: AUTHOR [+2]

Abstract

The use of 2's complement arithmetic allows the ability to handle negative biased exponents easily.

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Easy Biased Exponent Handling Via 2's Complement Arithmetic

The use of 2's complement arithmetic allows the ability to handle negative biased exponents easily.

In addition, the use of 2's complement arithmetic with 13 bits of exponent internal to the chip facilitates the detection of exponent underflows and overflows. In both precisions, single and double, only a few bits need to be examined to determine if underflow or overflow has occurred.

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If the exponent bias adjustment is done on the input to one of the operands on the exponent adder, the use of 2's complement arithmetic with 13 bits of exponent internal to the chip greatly simplifies the bias adjustment when the carry in of the adder is used. This bias subtraction for multiply and bias addition for divide becomes nothing more than a simple map.

In many IEEE Floating Point implementations two IEEE data formats are commonly used. These are Double and Single Precision. Each format consists of a sign, an exponent and a fraction field. Fig. 1 shows these data formats. The magnitude of a number is given by 2**(exponent - bias) times 1.fraction for normalized numbers.

In IEEE Floating Point Exponent calculations, the exponents are represented as biased numbers. This means that all valid exponents are represented as positive binary numbers for ease of handling. The implementation of exponent handling logic may include the bias in the calculations, but it is not necessary. The valid exponent range for single precision numbers is -125 to +126, and the valid exponent range for double precision numbers is -1021 to +1022. There are 8 bits for the single precision exponents and 11 bits for the double precision exponents. The table in Fig. 2 shows some examples of the relationship between biased exponents and their decimal values.

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Normalized numbers are the "normal" case numbers. They are represented in the IEEE format as a positive exponent with a leading B'1' in the fraction. Many algorithms require normalized operands to work properly.

Denormalized numbers are numbers that are too small to be represented in the exponent destination. They are created when the underflow exception is masked (i.e., not reported) and the exponent is too small to fit in the exponent destination. The fraction is shifted right and the exponent field is incremented until it is positive. Denormalized numbers are represented in the chip's hardware as an exponent of B'0000000000001', with a B'0' in the leading bit of the fraction.

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When the operand is prenormalized, the number of leading zeros is counted. This number is then subtracted from the exponent and the fraction is shifted left

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until a B'1' resides in the most significant bit of the fraction. Fig. 3 shows what happens to the exponent field when this subtraction takes place. Since there are 23 fraction bits for single precision and 52 fraction bits for double precision, the las...