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Simultaneous Definition of Two or More Patterns With One Multilevel Mask Structure

IP.com Disclosure Number: IPCOM000035810D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Cote, WJ: AUTHOR [+5]

Abstract

A technique for simultaneous definition of two metal levels in the fabrication of a semiconductor is shown that will produce a wiring level with a self-aligned stud level with one exposure.

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Simultaneous Definition of Two or More Patterns With One Multilevel Mask Structure

A technique for simultaneous definition of two metal levels in the fabrication of a semiconductor is shown that will produce a wiring level with a self-aligned stud level with one exposure.

A double level image is transferred into a metal film(s) making up two metal levels, i.e., the horizontal wiring level and the vertical stud level. A photoresist layer is formed having a thin-thick pattern, as shown in Fig. 1. The dark layers are tungsten, and the hatched layers are aluminum/copper. As shown in Fig. 2, the upper tungsten layer is etched in an etchant that does not attack the photoresist. This etch stops at the tungsten aluminum/copper interface. Then another etch is carried out to etch the aluminum/copper in an etchant that does attack the photoresist without attacking tungsten. As shown in Fig. 3, this has the effect of transferring the thin resist profile into the aluminum/copper layer. Then the first etchant is used again to attack the exposed tungsten shown in Fig. 4, and the aluminum/copper is etched again (the tungsten serving as the mask when the photoresist is completely eroded), as in Fig. 5.

The process sequence described defines two levels of metal, i.e., the wiring level and the stud level, or else a thick metal (low resistance) or a thin metal (low capacitance) structure. The relative absolute thickness of the bottom metal and the top metal is determined by the meta...