Browse Prior Art Database

Electroless Plating for Low-Cost High-Leverage Wiring

IP.com Disclosure Number: IPCOM000035814D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Cote, WJ: AUTHOR [+2]

Abstract

When conductor patterns are defined by etching troughs into insulators and filling the troughs with a conductor, the resulting vias to underlying conductors and troughs present a gapfill problem when their depth-to-width aspect ratios are greater than or equal to one. This article discloses a method that solves the gapfill problem.

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Electroless Plating for Low-Cost High-Leverage Wiring

When conductor patterns are defined by etching troughs into insulators and filling the troughs with a conductor, the resulting vias to underlying conductors and troughs present a gapfill problem when their depth-to-width aspect ratios are greater than or equal to one. This article discloses a method that solves the gapfill problem.

When conductor patterns are defined by etching troughs, and vias are formed down to an underlying conductor, the resist image used to etch the image into the insulator is left in place as shown in Fig. 1. Next an "electroless" (does not require a current) plating step is performed by utilizing an appropriate chemical dip to plate-up a stud with a low resistive metal, i.e., copper, aluminum, silver, etc. The plate-up nucleates only on the metal at the bottom of the vias and the thickness is chosen to be nearly coplanar with the trough surface. Next, a thin seed layer approximately 50 angstroms thick is deposited by appropriate means on the trough surface. Lift-off may be utilized or remove the resist, sputter metal, polish the top surface, apply a thin side wall oxide, etc. The nucleation layer in the trough is used to plate-up another material to be coplanar with the insulating surface material, as shown in Fig. 2. A two-step plating process is utilized to maintain planarity.

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