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Segmented Bit Line Architecture for Open and Folded Bit Line Cells

IP.com Disclosure Number: IPCOM000035822D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 119K

Publishing Venue

IBM

Related People

Sprogis, EJ: AUTHOR

Abstract

Both open and folded segmented bit line architectures are described for dense dynamic random-access memory cells. The global bit line for open bit line cells is on the same pitch as the bit line segment and connects sense amplifiers on either end while the global bit line for folded bit line cells is on two times the bit line segment pitch connecting sense amplifiers on either end. (Image Omitted)

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Segmented Bit Line Architecture for Open and Folded Bit Line Cells

Both open and folded segmented bit line architectures are described for dense dynamic random-access memory cells. The global bit line for open bit line cells is on the same pitch as the bit line segment and connects sense amplifiers on either end while the global bit line for folded bit line cells is on two times the bit line segment pitch connecting sense amplifiers on either end.

(Image Omitted)

The segmented open bit line architecture shown does not suffer from imbalance on end arrays and also results in lower bit line capacitance since it does not run through bit line support circuit areas. In addition, the scheme lays out in a very small area, requires simple controls to operate, and allows greater width section select devices, which are in series on the global bit line for improved signal development time on the bit line.

The end-to-end arrangement of sense amplifiers in this open and folded architecture allows the sense amplifier pitch to be double that of the conventional layout, greatly simplifying the layout. Other benefits of this scheme stem from the fact that the parasitic capacitance terms on the global bit lines are reduced significantly which results in greater signal while requiring less silicon area for pitch-limited support circuits.

Referring to Figs. 1 and 2, each sense amplifier is serviced by bit switches and decoders, with interior sense amplifiers able to share double-ended decoders. The global bit line does not extend through the bit switch decoder area. A series device (T1) on the global bit line, placed between bit line segments 1 and 2, 3 and 4, etc., divides the global bit line into two sections when un- selected (off). Selection criteria is simply when a word line is selected in either left or right segments adjacent to T1. All other series devices are selected (on). Note that depending on which series device has been opened, the bit line capacitance (although balanced) may be different between left and right sense amplifier sides.

A bit lin...