Browse Prior Art Database

Total Incorporation of Tie Up/Down Feature Into FCMI Multiplexer Design

IP.com Disclosure Number: IPCOM000035827D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Staddon, D: AUTHOR

Abstract

Traditional CMOS multiplexer designs do not require the select lines to be mutually exclusive, but run the risk of requiring potentially high stacks which degrade performance. A basic FCMI multiplexer design reduces the risk of potentially high stacks, but requires the select lines to be mutually exclusive. Through a hybrid combination of these multiplexer design approaches, the overall performance is improved and the tie up/down feature is internal to the FCMI multiplexer without requiring the tie up/down pin to be mutually exclusive with the other select pins, at a minimal to zero increase in size.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Total Incorporation of Tie Up/Down Feature Into FCMI Multiplexer Design

Traditional CMOS multiplexer designs do not require the select lines to be mutually exclusive, but run the risk of requiring potentially high stacks which degrade performance. A basic FCMI multiplexer design reduces the risk of potentially high stacks, but requires the select lines to be mutually exclusive. Through a hybrid combination of these multiplexer design approaches, the overall performance is improved and the tie up/down feature is internal to the FCMI multiplexer without requiring the tie up/down pin to be mutually exclusive with the other select pins, at a minimal to zero increase in size.

The examples shown in the figures specifically refer to 3:1 multiplexers with the tie up or tie down feature; however, the design modifications shown also apply to 2:1, 4:1 and 5:1 multiplexer designs with tie up/down features.

Fig. 1 shows the current design of a 3:1 multiplexer with a tie up feature. If pin V1 (tie up pin) is "on" (equal to 0) and any of the select pins (S0, T0 and U0) are "on" (equal to a 1), then the circuit will short. Therefore, external logic is required to guarantee that the select pins are "off" when the tie up pin is "on". This results is a degradation in performance. By modifying the circuit as shown in Fig. 2, the external constraint requiring V1 to be mutually exclusive with S0, T0 and U0 avoids the shorting problem.

Fig. 3 shows the current design of a 3:1 multiplex...