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Counter Control Subsystem for the Functional Self Test Chip Prototype

IP.com Disclosure Number: IPCOM000035829D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Chan, GK: AUTHOR [+2]

Abstract

This article describes the functions of the counter control subsystems for the functional self-test chip (FSTC) prototype.

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Counter Control Subsystem for the Functional Self Test Chip Prototype

This article describes the functions of the counter control subsystems for the functional self-test chip (FSTC) prototype.

There three functions performed by the counter control subsystem are CLEAR, LOAD and COUNT.

During normal data acquisition involving counters, the counters are first cleared by the clear counter signals (+CLR0 and +CLR1). Then, the counters are loaded with the number of wait and acquisition cycles. When the data acquisition enable (ACQ_EN) is activated, the counter count enable (CPU0 and CPU1) signals will become active and remain active until the counters count down to zero.

Either a system reset or counter clear encoding will generate the clear counter (+CLR0 and +CLR1) signals. +CLR0 is for counter 0 and (+CLR1) is for counter 1. +CLR0 = system reset + clear counter 0 +CLR1 = system reset + clear counter 1

The control logic will generate the load counter enable (-LD0 and -LD1) signals, when the load counter command is received by the control register. The (-LD0 and -LD1) signals will enable the counters to load the contents on the data bus to the counter asynchronously. -LD0 = load counter 0 -LD1 = load counter 1

When the acquisition enable (ACQ_EN) is received, the count enable (CPU0 and CPU1) will be activated with the following conditions: +CPU0 = acquire using one counter * acquisition enable activated *

counter

0 has not reached zero

+ acquire using two counter * ac...