Browse Prior Art Database

Functional Self Test Chip Instruction Encoding

IP.com Disclosure Number: IPCOM000035831D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Huntington, NL: AUTHOR [+4]

Abstract

The instruction encoding for the functional self-test chip (FSTC) is designed to simplify application specific interfacing hardware.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Functional Self Test Chip Instruction Encoding

The instruction encoding for the functional self-test chip (FSTC) is designed to simplify application specific interfacing hardware.

All instructions are one 16-bit word in length. Selected instructions require subsequent data transactions.

The encoding consists of two fields each of which are composed of two sub- fields. The first field is the function which encompasses the instruction and the device. The second is an internal address consisting of bank and line selects.

The encodings are listed below.

1

Page 2 of 2

2

[This page contains 7 pictures or other non-text objects]