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Set of Stress Tests for Evaluating Serialized Optical Data Links

IP.com Disclosure Number: IPCOM000035837D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Myers, WV: AUTHOR [+2]

Abstract

A method is needed for stressing the clocking mechanisms in serialized optical data links to evaluate design weaknesses and allow performance comparisons of different designs.

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Set of Stress Tests for Evaluating Serialized Optical Data Links

A method is needed for stressing the clocking mechanisms in serialized optical data links to evaluate design weaknesses and allow performance comparisons of different designs.

The main approach for evaluating such links so far is to attenuate the optical signals, which reduces signal-to-noise ratio, and to cause jitter of the received serial data relative to its retiming clock. Using long optical links also adds dispersion to the optical pulses, further increasing jitter in the retiming process. These approaches do not accentuate subtle design differences or weaknesses though and do not allow control of different types of stress mechanisms. Also, there is no present method for testing the response to the displacement of a single bit.

The desired results are achieved using three different kinds of stress on the input data block to the link: 1. Frequency Shifting 2. Phase Shifting 3. Single- Pulse Shifting

The first two are shifts that last for long enough periods for the link circuitry to completely respond to the shift and obtain a new operating point. The third is short enough that the link operating point should not change.

As seen in Fig. 1, there are two phase-locked loops (PLLs) in the link circuitry which need to be stressed. Stresses on PLL1 must not be drastic enough to cause clocking errors in the serializer circuitry. Rather, their effect is mainly felt in the way that the Retiming PLL responds to phase or frequency differences in the Serial Data on the Optical Data Link.

Fig. 2 shows Input Clock waveforms for the three types of stress. Waveform A shows Frequency Shifting of the Input clock at t1, and a return to the original frequency at t2. This frequency shift will be responded to gradually in PLL1, and Ck2 will eventually be in phase with the Input Clock again. While this is happening, though, the Retiming PLL's frequency will take time to respond to the frequency change of the Seria...