Browse Prior Art Database

Concurrent Double Level Wiring Process

IP.com Disclosure Number: IPCOM000035853D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR [+2]

Abstract

Two levels of wiring are formed in an insulator stack by means of two mask areas passing two levels of light flux to expose a single photoresist and use of etch stop (ES) layers in the insulator stack. Improved wiring density is obtained from resultant improved planarization and, when a single gray level mask is used for definition of the two wiring levels, a further wiring density improvement is obtained. (Image Omitted)

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Concurrent Double Level Wiring Process

Two levels of wiring are formed in an insulator stack by means of two mask areas passing two levels of light flux to expose a single photoresist and use of etch stop (ES) layers in the insulator stack. Improved wiring density is obtained from resultant improved planarization and, when a single gray level mask is used for definition of the two wiring levels, a further wiring density improvement is obtained.

(Image Omitted)

Referring to Fig. 1, a first insulator layer 2 is planarized and coated with ES layer 4. A second insulator layer 6 and a second ES layer 8 are deposited next followed by deposition of a third insulator layer 10 and ES layer 12. Then positive photoresist (PR) layer 14 is applied, dried and exposed to light flux sufficient to make the full depth of PR 14 soluble in developer for the pattern of a lower wiring level. A reduced light flux level is used to expose a pattern of an upper wiring level in PR 14. The two flux levels may be achieved by using a single, gray level mask or by using two masks with different exposure fluxes applied through each mask. The structure of Fig. 1 is completed by developing PR 14.

Referring to Fig. 2, the pattern of the lower metalization level is successively reactive ion etched through layers ES 12, insulator 10, ES 8, and insulator 6 by appropriate changes of etch gas. ES 4 stops the etching and allows complete removal of insulator layer 6. Reactive ion etching with an oxidizing etch gas is used next to reduce the thickness of PR 14 sufficiently to expose the surface of ES 12 in all areas of the upper level wiring pattern. ES 12 and insulator 10 are then etched, thus projecting the upper wiring level pattern through insulator 10 and stopping at ES 8. Remaining PR 14 is removed to complete the structure shown in Fig. 2.

Referring now to Fig. 3, by methods, e.g. vacuum depositing a nucleating layer on all horizontal surfaces and then planarizing to remove...