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Cyclic Redundancy Check Control Subsystem for the Functional Self-Test Chip (Fstc) Prototype

IP.com Disclosure Number: IPCOM000035856D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Chan, GK: AUTHOR [+3]

Abstract

The control system described in this article serves to control the cyclic redundancy check (CRC) data acquisition, data compression, and signature read modes designed for the functional self-test chip (FSTC) prototype.

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Cyclic Redundancy Check Control Subsystem for the Functional Self-Test Chip (Fstc) Prototype

The control system described in this article serves to control the cyclic redundancy check (CRC) data acquisition, data compression, and signature read modes designed for the functional self-test chip (FSTC) prototype.

The CRC circuits implemented in the FST chip prototype board are Signetic CRC Checker 9401. The detailed operations of the 9401 is listed in the Signetic Bipolar LSI Products Manual - 1986.

The control logic will perform the following: 1. Clear the CRC internal registers prior to data acquisition. It can be accomplished by pulling the master reset of the CRC low. 2. Generate the clock signal and hold the CWE high for data acquisi tion. The data will be shifted in serially at the trailing edge of the clock. 3. Generate the clock signal and hold the CWE low for 16 clock cycle so that the 16-bit signature can be serially shifted out into a serial in/parallel out register buffer. The function of each block is described below. CRC Clear

Eight active low clear signals (cclr_1 to cclr_8) are generated asynchronously when the clear encoding from the FST control register is received. All eight signals are identical. Eight clear signals are needed because of fan_out requirements. The reduced equation for cclr_1 is listed below. cclr_1 = clear * crc + clear * all CRC Clock Generator

CRC clock signals are required for both data acquisition mode and signature read mode. In the asynchronous acquisition mode, the CRC clock is the results of gating board under test's (BUT's) clock with the control encoding and the acquistion en...