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Circuits Performing Four "Two-Way" Random Logic Functions With Three Input Pins for Optimized Use of Spare Pins of Gate Arrays

IP.com Disclosure Number: IPCOM000035861D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Verhaeghe, M: AUTHOR

Abstract

Disclosed are two circuits providing an optimized use of spare signal pins of ASICs (Application Specific Integrated Circuits).

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Circuits Performing Four "Two-Way" Random Logic Functions With Three Input Pins for Optimized Use of Spare Pins of Gate Arrays

Disclosed are two circuits providing an optimized use of spare signal pins of ASICs (Application Specific Integrated Circuits).

The circuits have 3 inputs and 1 output, all of them connected to unused signal pins of the ASICs via appropriate receiver and driver circuits.

The inputs being named X, A, and B, the two circuits provide the following boolean functions: First circuit Output = X . A + X- . B- Second circuit Output = X . A- + X- . B where . stands for logical AND, + for logical OR, X- for complement of X.

According to the ASIC technology, these two circuits can be built with conventional AND, OR, inverter circuits or more complex combinations of devices.

By connecting A or B inputs to a permanent down or up level, or connecting 2 inputs together, the first circuit provides the four "two- way" logic functions AND, NOR, XOR complement and OR with one inverted input.

In the same way, the second circuit provides the four "two-way" logic functions OR, NAND, XOR and AND with one inverted input.

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