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Lightly Doped Drain Structure With Reduced Series Resistance to Device Channel

IP.com Disclosure Number: IPCOM000035873D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+2]

Abstract

By means of a dual salicide process, electrical resistance between a source or drain contact and the device channel of a lightly doped drain (LDD) device is reduced, thereby improving device performance.

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Lightly Doped Drain Structure With Reduced Series Resistance to Device Channel

By means of a dual salicide process, electrical resistance between a source or drain contact and the device channel of a lightly doped drain (LDD) device is reduced, thereby improving device performance.

Referring to Fig. 1, standard processing is used to make recessed oxide (ROX) region 2 and polysilicon gate line 4 having a thin sidewall spacer 6 disposed over gate insulator 8 on substrate silicon 10. A first thin layer of cobalt (Co) metal is then deposited and annealed to form cobalt monosilicide (CoSi) 12 in contact openings and CoSi 14 on the top of gate line 4. Unreacted Co is etched away. An ion implant is used to create a shallow, lightly doped junction region 16 and also places the impurity in gate conductor 4, region 18 (without consequence), to complete the structure of Fig. 1.

Referring now to Fig. 2, a thicker sidewall spacer 20 is made, a second thicker Co layer is deposited and annealed to form cobalt disilicide (CoSi2) 22 in the contact region and CoSi2 24 on top of gate line 4. Again, residual Co is etched off. A second, higher dose impurity implant is made to place the impurity entirely within the thickness of CoSi2. An anneal uniformly distributes the impurity throughout the CoSi2 and polysilicon of gate line 4 before diffusion into the substrate silicon takes place. A graded junction 26 is thus formed in substrate 10 which is directly connected to highly conductive...