Browse Prior Art Database

GATE Quality Tests at Polysilicon Etch Step on CMOS Products

IP.com Disclosure Number: IPCOM000035878D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Chassagne, F: AUTHOR [+3]

Abstract

The polysilicon-to-substrate test is performed after polysilicon etch to find gate oxide defects on a test site. There are 2 serpentines above the P type epitaxy area and 2 serpentines above the N-Well area. These serpentines are running on the gate thin oxide. A bias of 7.5 volts is applied to both types of polysilicon gates with an automatic tester; the substrate is biased at the back of the wafer to ground. If the current is greater than 1 micro A, there is evidence of a poly-to- substrate short; if the current is less than this value, the gate chain is good. The test is performed on each lot, e.g., 5 wafers by lot, 3 test sites by wafer. The defects found with the test site are more defect density related. The line monitoring is done by yields; a good lot has more than 95% yield.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 2

GATE Quality Tests at Polysilicon Etch Step on CMOS Products

The polysilicon-to-substrate test is performed after polysilicon etch to find gate oxide defects on a test site. There are 2 serpentines above the P type epitaxy area and 2 serpentines above the N-Well area. These serpentines are running on the gate thin oxide. A bias of 7.5 volts is applied to both types of polysilicon gates with an automatic tester; the substrate is biased at the back of the wafer to ground. If the current is greater than 1 micro A, there is evidence of a poly-to- substrate short; if the current is less than this value, the gate chain is good. The test is performed on each lot, e.g., 5 wafers by lot, 3 test sites by wafer. The defects found with the test site are more defect density related. The line monitoring is done by yields; a good lot has more than 95% yield.

The gate integrity test is performed to find gate oxide defects on a large kerf capacitor. The capacitor has an area of about .1 mm and is located above the P epitaxy. The defects found by the gate integrity test are more 'volume' related, but this test matches well with the previous test for 0 hours defects. A negative ramp from 0 to -40 volts is applied on the gate with .1 volt by step. If the current is greater than 5 micro A, the oxide break-down voltage VBD is recorded. Depending on its value, the following table shows the type of defect: VBD 0 to 5 V ====> 0 hrs defects (Pinhole)

VBD 5 to 25 V ====> oxide break-down d...