Browse Prior Art Database

High-Performance Vertical Npn With Soi Lateral Pnp

IP.com Disclosure Number: IPCOM000035898D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Li, GP: AUTHOR [+3]

Abstract

Disclosed is a novel approach for integrating a high-performance lateral pnp with a high-performance "double-poly" vertical npn for complementary bipolar circuit applications. The high-performance lateral pnp device is achieved through a buried oxide layer underneath the lateral pnp to reduce parasitic capacitance and base charge storage.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 68% of the total text.

Page 1 of 2

High-Performance Vertical Npn With Soi Lateral Pnp

Disclosed is a novel approach for integrating a high-performance lateral pnp with a high-performance "double-poly" vertical npn for complementary bipolar circuit applications. The high-performance lateral pnp device is achieved through a buried oxide layer underneath the lateral pnp to reduce parasitic capacitance and base charge storage.

The fabrication process is implemented as follows. The p- substrate is used as in the conventional bipolar substrate wafer. A thin layer of oxide is grown first. A mask is then used to implant the n++-buried sub-collector layer and to form the insulator islands 1, as shown in Fig. 1a of the final device cross section. The channel stop boron implant is then performed to have p+ region 2 underneath the oxide islands, as shown in Fig. 1a. This can be done by blanket I/I, since the boron dose is low. Epitaxy growth of the f-epi from the exposed silicon surface with lateral overgrowth is used to form a continuous single crystalline silicon layer 3 over the oxide islands, as shown in Fig. 1a. Note that the oxide islands can be partitioned such that the pattern width w is less than two times the epitaxy thickness t in order to form a continuous film in the overgrowth layer. The n++ buried layer and f-epi are used for building the vertical npn device in the usual manner, and the final device cross section is as shown in Fig. 1b. The oxide island and f-epi are used for fabricating the la...