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Borderless Gate Contacts for CMOS Applications

IP.com Disclosure Number: IPCOM000035904D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Bajuk, S: AUTHOR [+6]

Abstract

As the gate count increases and the device size decreases in CMOS VLSI logic chips, the wiring contribution to the overall chip performance becomes more and more important. This is especially true in gate arrays where wiring constraints are the largest. A huge development effort is aimed at the minimization of wiring length through improved process (reduced metal pitch, three-level metallization) and improved placement and wiring algorithms.

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Borderless Gate Contacts for CMOS Applications

As the gate count increases and the device size decreases in CMOS VLSI logic chips, the wiring contribution to the overall chip performance becomes more and more important. This is especially true in gate arrays where wiring constraints are the largest. A huge development effort is aimed at the minimization of wiring length through improved process (reduced metal pitch, three-level metallization) and improved placement and wiring algorithms.

Standard CMOS processes used in gate arrays can be modified to provide more compact cells and facilitate book placement and wiring. The change allows first metal/poly-Si gate contacts to be opened any

(Image Omitted)

where on the gate itself, and eliminates the necessity of large polysilicon extensions on the filed oxide seen in standard designs. In Fig. 1, we show the 3 possible gate contact positions (on horizontal tracks) on a conventional CMOS gate array (left part). This is to be contrasted with the new approach (right part), without any design change, that allows 11 contact positions. This results in improved wiring capabilities both locally and globally. An alternate design using fully a borderless contact would be to remove completely the poly heads, which would define a smaller cell size.

The process used as an example here is a standard submicron CMOS process which includes spacer formation for drain engineering purposes. We keep all the process steps unchanged up to the S/D implant screen oxide str...