Browse Prior Art Database

Programmable Pattern Buffer Size

IP.com Disclosure Number: IPCOM000035908D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Dubler, JF: AUTHOR [+2]

Abstract

Disclosed is a method that permits software to control the assignment of pattern buffer memory modules to designated pins in a physical modeler. Generally, hard wired, fixed memory is assigned to each pin in a physical modeler which results in inefficient utilization of that memory. Compressing patterns via algorithmic op codes, repeat counts, or change only data results in each pin's having its own pattern buffer size requirements. The disclosed technique enables a physical modeler to utilize the unused input pattern buffers allocated to pins configured as pure output nets. Also, physical devices that are operated in "static" mode could relinquish possession of all their pattern buffer memory, which could then be utilized by other pins which require additional memory.

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Programmable Pattern Buffer Size

Disclosed is a method that permits software to control the assignment of pattern buffer memory modules to designated pins in a physical modeler. Generally, hard wired, fixed memory is assigned to each pin in a physical modeler which results in inefficient utilization of that memory. Compressing patterns via algorithmic op codes, repeat counts, or change only data results in each pin's having its own pattern buffer size requirements. The disclosed technique enables a physical modeler to utilize the unused input pattern buffers allocated to pins configured as pure output nets. Also, physical devices that are operated in "static" mode could relinquish possession of all their pattern buffer memory, which could then be utilized by other pins which require additional memory.

One implementation of this method uses first-in, first-out (FIFO) memory modules for the pattern buffers. This eliminates the problem with hard-wired memory addresses. Since FIFOs act like shift registers, it is simple to multiplex the SERIAL OUT (SO) nets to SERIAL IN (SI) nets to daisy-chain the memory modules to the desired depth. Fig. 1 illustrates a basic cell that is repeated for each FIFO memory module. The daisy-chained memory is then connected to the pin drivers and level detectors, as shown in Fig. 2. This basic cell is repeated for each pin in the tester or physical modeler.

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