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Technique for an Array Reset at High Speed

IP.com Disclosure Number: IPCOM000035926D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Feeney, JW: AUTHOR

Abstract

Resetting of an array to initial values takes a very long time when compared to simulation time. The following technique achieves this reset with high speed.

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Technique for an Array Reset at High Speed

Resetting of an array to initial values takes a very long time when compared to simulation time. The following technique achieves this reset with high speed.

Briefly, it must be recognized that to achieve a reset of an array at a higher speed than usual, it must be accomplished without halting the simulation run. Three copies of the array are utilized. The original, or master, array M is never modified. The other two copies A and B are attached alternatively to the model and to the reset logic. While the array A that is attached to the model is being updated, the second array B is reset from the original master M. To reset the model, it is connected to the array that was just reset, i.e., the array B. Then, the array A is connected to the reset logic. This is done by select logic that is added to the model. Then, while simulation continues, the second array B is updated and the first array A is reset. To reduce the reset time still further, only the addresses changed in the array are reset.

The following step-by-step technique will achieve a rapid reset of array M between simulation runs:

1. Add two additional copies of array M (A & B), two address arrays (Aa & Ba), two counters (Ac & Bc), select logic, and reset logic to the model.

2. Initialize counters Ac & Bc to 0.

3. Prior to simulation, connect the array A to the model via the select logic, and connect the array B to the reset logic.

4. During simulation, anytime a WRITE occurs to array A, write the address into array Aa and increment the counter Ac. If Ac exceeds the depth of Aa, then this process is inhibited.

5. When the reset is to be done, connect the array B to the model, and connect the array A to the reset logic.

6. During simulation, the array B will be used by the model, and any WRITE addresses will be collected in Ba & Bc.

7. At the same time, the reset logic will read the master array data from the array M and will write it back to the array A. This will occur in one of three ways (steps 8, 9 or 10).

8. If the counter Ac = 0, no reset will be done.

9. If the counter Ac starts out less than or equal to the depth of the array Aa, then the counter Ac will be used to read...