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High-Performance Non-Saturating Complementary NTL Circuits

IP.com Disclosure Number: IPCOM000035927D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Chuang, CK: AUTHOR

Abstract

A technique is described whereby a non-saturating complementary non- threshold logic (NTL) circuit provides low power and high performance, by using complementary emitter-follower drivers, so as to avoid saturation. The concept is an improvement over traditional emitter-follow er drive circuits, which are limited by their pull-down resistors.

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High-Performance Non-Saturating Complementary NTL Circuits

A technique is described whereby a non-saturating complementary non- threshold logic (NTL) circuit provides low power and high performance, by using complementary emitter-follower drivers, so as to avoid saturation. The concept is an improvement over traditional emitter-follow er drive circuits, which are limited by their pull-down resistors.

High-performance complementary bipolar circuits are typically implemented, so as to reduce power consumption, to enhance current- driving capability and to reduce loading dependency of the gate delay. However, the traditional emitter- follower drivers used in bipolar circuits consume considerable amounts of power and the speed is limited, due to the pull-down resistor. Also, PNP (push)-NPN- (pull) drivers must saturate in order to assure a stable operating point for the output. The saturation charge storage severely limits the speed of the device. The concept described herein is a complementary emitter- follower driver, in the complementary NTL circuit, such that none of the transistors ever saturate, thereby providing low power and high speed operation.

(Image Omitted)

The concept's basic complementary NTL inverter circuit is shown in Fig. 1. It utilizes capacitors 10 and 11 as speed-up capacitors.

The operation of the circuit is as follows: A) When the input goes "High", transistor 16 turns on

and transistor 17 turns off. The voltage at node

"A" assumes the "Low" value due to the IR drop

through the collector load resistor 18. The

voltage at node "B" assumes the "Low" value, since

there is no current flowing through transistor 17.

Due to the complementary emitter- follower driver,

the output assumes the intermediate value between

nodes "A" and "B" and therefore the output is

"Low."

B) When the input goe...