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Method for Making Self-Aligned, Reverse-T Gate LDD Mosfet

IP.com Disclosure Number: IPCOM000035931D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Hsu, CH: AUTHOR [+2]

Abstract

Disclosed is a fabrication method for making a reverse-T gate LDD structure by a self-aligned technique.

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Method for Making Self-Aligned, Reverse-T Gate LDD Mosfet

Disclosed is a fabrication method for making a reverse-T gate LDD structure by a self-aligned technique.

One of the problems encountered with the submicron CMOS VLSI has been the device reliability due to the hot electron effect in the device with very small channel length. A device with a lightly doped drain (LDD) has been proven to be the adequate way to increase device hot electron reliability. However, when device channel length is scaled down to below half a micrometer, the traditional technique for fabricating LDD devices is not suitable any more because the short channel effect may encounter if the lightly doped drain is over- diffused into the gate overlap region or the series resistance may increase drastically if the lightly doped region is not overlapped properly with the gate. The reverse-T gate structure has been shown to solve this problem [*], but the etch stop process is not suitable for the manufacture purpose because of the non-uniform nature of both the CVD and RIE processes, as well as the difficulty of the process control. The disclosed method can solve this problem in a self- aligned manner.

The disclosed method is shown in the figure. First, the MOS device is fabricated to the poly gate formation, followed by the LDD implantation. Then a thin polysilicon film (second poly) is deposited, followed by a dielectric film (oxide or nitride) deposition for sidewall formation. Then the devic...