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Browse Prior Art Database

64-Bit Structured Partial Decoded Shifter Circuit

IP.com Disclosure Number: IPCOM000035932D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Desrosiers, B: AUTHOR [+2]

Abstract

The principle of this shifter circuit lies on the separation of the 64 bits into eight groups of eight bits each. Shift is performed in going through the two stages of the shifter: Stage 1 : Shifts 0 to 7 groups of 8 bits Stage 2 : Shifts 0 to 7 bits

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64-Bit Structured Partial Decoded Shifter Circuit

The principle of this shifter circuit lies on the separation of the 64 bits into eight groups of eight bits each. Shift is performed in going through the two stages of the shifter: Stage 1 : Shifts 0 to 7 groups of 8 bits

Stage 2 : Shifts 0 to 7 bits

Note that stage 1 and stage 2 are identical. Because of this separation (8 groups of 8 bits) it is possible to control separately the two stages in a very simple way; it is not necessary to completely decode the shift amount, but just to take the three LSBs (Least Significant Bits) of the shift amount to control the "bit" stage and the three MSBs (Most Significant Bits) of the shift amount to control the "group" stage.

The attached drawing shows a typical example, where in order to shift 36 bits, the shift amount is 1 0 0 1 0 0.

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