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Fabrication Method to Offset the Self-Aligned Vertical Connection Over the Trench Capacitor

IP.com Disclosure Number: IPCOM000035935D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 177K

Publishing Venue

IBM

Related People

Lu, NCC: AUTHOR [+2]

Abstract

This publication describes a new design and fabrication technique to offset the self-aligned vertical connection over the trench capacitor to minimize the stacked DRAM cell size.

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Fabrication Method to Offset the Self-Aligned Vertical Connection Over the Trench Capacitor

This publication describes a new design and fabrication technique to offset the self-aligned vertical connection over the trench capacitor to minimize the stacked DRAM cell size.

A self-aligned epitaxial contact formation process is known in the art for forming a vertical connection between the trench capacitor

(Image Omitted)

Next, the trench is filled with p+ poly by CVD and then planarized. An oxide layer with suitable thickness is grown locally over the trench capacitor (Fig. 2).

(1-2) The nitride and pad oxide layers are removed to expose the large single crystal region surrounding the oxide covered trench capacitor. Then an epitaxial single crystal film is grown with controlled lateral epi growth over the oxide region by controlling the vertical epi growth to leave a hole in the middle of the trench capacitor (Fig. 3).

(Image Omitted)

(1-3) By using the silicon epi layer as a mask, the oxide over the trench is removed only in the opening area (Fig. 4).

(1-4) Then a second epi layer is used to fill the hole. Since the poly inside the trench is exposed to the second epi growth, a low-quality epi region is formed vertically, as shown in Fig. 5.

(1-5) Then the shallow oxide trench isolation, the n-well, and poly gate are formed, as shown in Figs. 6 and 7.

(1-6) The source/drain region of the transfer device is then formed by a shallow ion implantation. Because of the high diffusivity of the low quality vertical epi region, a p+ connection between the source region and the poly inside the trench is formed through subsequent temperature cycles, as shown in Fig. 7. This vertical connection is called the "neck" in the following. Then the standard CMOS process is resumed to complete the cell structure.

Fig. 8 shows both the top and side views of two SSPT cells. The neck is formed at the center of the trench capacitor because of uniform growth rate of the lateral epi. However, in order to achieve a small cell size with the same trench capacitor, it is desirable to offset the neck from the center to the edge of the trench capacitor away from the gate region (Fig. 9). By doing so, the lateral diffusion from the neck will not degrade the transfer device short channel effect as much as the case with the neck at the center. Disclosed here is a new fabrication technique to achieve the neck offset.

The new fabrication procedures are described in the follow...