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New Vertical Stacked-Transistor Substrate-Plate Trench Cell and Fabrication Process Therefor

IP.com Disclosure Number: IPCOM000035938D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Lu, NCC: AUTHOR [+2]

Abstract

This publication describes a new vertical stacked-transistor substrate- plate cell and the fabrication process therefor. The stacked transistor has a vertical conducting channel on top of the trench capacitor. The cell cross section is shown in Fig. 1, and the top view in Fig. 2. The trench capacitor is formed by using n+ epi material to fill the trench so that MOS capacitors are obtained on the four sidewalls and an n+/n/p+ junction capacitor on the bottom. The trench bottom opening provides the seed for growing epi material. The stacked transistor has a vertical conducting channel on top of the trench capacitor.

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New Vertical Stacked-Transistor Substrate-Plate Trench Cell and Fabrication Process Therefor

This publication describes a new vertical stacked-transistor substrate- plate cell and the fabrication process therefor. The stacked transistor has a vertical conducting channel on top of the trench capacitor. The cell cross section is shown in Fig. 1, and the top view in Fig. 2. The trench capacitor is formed by using n+ epi material to fill the trench so that MOS capacitors are obtained on the four sidewalls and an n+/n/p+ junction capacitor on the bottom. The trench bottom opening provides the seed for growing epi material. The stacked transistor has a vertical conducting channel on top of the trench capacitor. The transistor source region is formed by the out-diffusion of ndopants from the epi film inside the trench, and the drain region is

(Image Omitted)

obtained by the diffusion of dopants from the n+ poly bitline on the top of the transistor. The wordline is formed by a salicided n+ layer using lateral epi growth over the trench capacitor. The body of the transistor is single crystal silicon formed by selective epi technique using epi film inside the trench as seeding material. The significant difference over the prior art * is that the single-crystal body of the transistor is obtained from an epi technique instead of requiring a recrystallization technique. The recrystallization technique usually causes large lateral diffusion of the dopants, and is not practical for realizing such a small-size memory cell. The other difference is to use the n+ diffusion layer as a wordline to avoid the complexity of making a polysilicon wordline on both sides of the transistor channel;

(Image Omitted)

the transistor is isolated by the thin gate oxide and wordline (Fig. 2). The transistor can be designed for either enhancement mode or depletion mode. For enhancement mode, the body is medium-doped p-type material and the conduction between the source and drain regions is through the four surface channels under the thin gate oxide. The depletion-mode operation can be fabricated using medium-doped n-type body material. The transistor is turned off by using pinch-off due to the extension of the depletion layers formed from four sidewalls of the transistor and turned on by decreasing the depletion-layer width such as by applying negative voltage across the gate to the source or drain region.

(Image Omitted)

The fabrication procedures for this new cell are as follows:

(1) Using nitride and oxide as a mask, a deep trench is made in a p- on p+ epi wafer with steep sidewalls by RIE. The thin storage insulator is formed on the trench sidewalls by using oxide/nitride/ oxide composite material (Fig. 3).

(2) RIE is used to remove the storage insulator at the bottom of the t...