Browse Prior Art Database

Planar/Processor Interface for Personal Systems

IP.com Disclosure Number: IPCOM000035941D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 138K

Publishing Venue

IBM

Related People

Begun, RM: AUTHOR [+3]

Abstract

A technique is described whereby a personal system, such as the IBM PS/2, is architecturally configured to enable subsystem expansion and/or enhancement capabilities through the incorporation of a daughter circuit card. A planar/processor interface is designed to allow subsystem applications where a normal planar circuit board does not have sufficient space to incorporate a subsystem. A typical example would be the incorporation of a cache subsystem that is designed to increase the performance of memory.

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Planar/Processor Interface for Personal Systems

A technique is described whereby a personal system, such as the IBM PS/2, is architecturally configured to enable subsystem expansion and/or enhancement capabilities through the incorporation of a daughter circuit card. A planar/processor interface is designed to allow subsystem applications where a normal planar circuit board does not have sufficient space to incorporate a subsystem. A typical example would be the incorporation of a cache subsystem that is designed to increase the performance of memory.

In prior systems, the normal planar circuit board would not have sufficient space to incorporate the circuitry needed for the cache. For example, a typical 64K-byte cache requires approximately twenty square inches of board space to accommodate the static random-access memory (SRAM), buffering and control logic circuitry. The concept described herein reconfigures the architecture of the system to provide for the enhancement of cache memory operation.

The isolation of the CPU/Cache complex, in this case, is implemented for the following reasons: The CPU local bus will support address and data transfers independently of the system bus when utilizing the cache memory or a math co- processor. This effectively reduces bus traffic at the interface. The physical size of the daughter card, as in the case of a CPU/Cache subsystem, can be reasonably contained. Only the daughter card needs to be replaced in the event the subsy...