Browse Prior Art Database

Slow Speed Data CARD for Automotive Engine Test Data Acquisition

IP.com Disclosure Number: IPCOM000035970D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 4 page(s) / 112K

Publishing Venue

IBM

Related People

Bou-Ghannam, A: AUTHOR [+4]

Abstract

This article concerns a slow speed data card (SSDC) which provides an effective means of acquiring specific data from an automotive vehicle and provides for correlation of the data with data acquired by other means for the purpose of engine performance analysis.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 4

Slow Speed Data CARD for Automotive Engine Test Data Acquisition

This article concerns a slow speed data card (SSDC) which provides an effective means of acquiring specific data from an automotive vehicle and provides for correlation of the data with data acquired by other means for the purpose of engine performance analysis.

SSDC is one of two attachment cards in an automotive engine analyzer. The engine analyzer interfaces a personal computer (PC) as a host.

The function of the SSDC is to collect and process the following engine data from vehicle test interface circuits and to save the results for the host.

(Image Omitted)

.

1. Dynamic ignition data

a. top dead center (TDC) signal (from engine

flywheel)

b. points close signal

c. points open signal (TD)

d. spark data ready

2. Static data readings from up to sixteen

analog-to-digital (A/D) converters (including

emissions and peak spark voltage)

The SSDC is made up of the major blocks shown in Fig. 1. A greater level of detail is provided in Fig. 5. The SSDC has commonality with the high speed data card (HSDC) in the following areas:

Bus interface

RAM (Bank O and Bank 1)

Memory Interface

The SSDC processor is an Intel 8052 family microcontroller which has the following features:

8-bit CPU

8K bytes of ROM

256 bytes of RAM

32 I/O lines

(Image Omitted)

Three 16-bit timers/counters

Full duplex serial port

The main differences between the HSDC and the SSDC are in the area of the interface to the vehicle test circuits. The ignition data interface block shown in Fig. 1 and detailed in Fig. 4 includes an edge-triggered D flip-flop which is used to gate a counter in the

1

Page 2 of 4

8052 for ignition voltage rise-time measurements. In addition, a logic gate allows two input signals to interrupt the microcontroller at interrupt (INT1). Another interface on the SSDC is to the A/D converters which are addressed and read by the SSDC. The A/D interface consists of:

(Image Omitted)

.

4 address lines to select 1 of sixteen 16-bit A/D

converters

1 data ready line indicating that data is waiting to

be read

Circuitry supporting the A/D functions (address select, handshake, and data transfer from A/D output to RAM) are in the A/D interface shown in Figs 1 and 5.

The engine analyzer timing is illustrated in Fig. 2 for a four cylinder engine. The drawing shows the signals relevant to the SSDC that occur during a single 360-degree revolution of the crankshaft and flywheel. As the engine turns, the signals appear in the following sequence for collection and processing:

1) TDC signal causes a timer to be reset and

restarted by an interrupt service routine

through the INT2 input of the micocontroller.

During other specific events the timer value

is saved in RAM to mark the events.

2) Points close signal, and points open signal

(TD) use INT1 to start interrupt service

routines to save the timer value of the

events in RAM. The two inputs are tested by

the microcontrollers to determine which

signal caused the...