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Browse Prior Art Database

Logically Controlled Chip Interconnection Technique

IP.com Disclosure Number: IPCOM000035975D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 5 page(s) / 116K

Publishing Venue

IBM

Related People

Najmann, K: AUTHOR [+4]

Abstract

A silicon wiring wafer 1 is used as a carrier for chips 2 and as a chip interconnection means (Fig. 1). The interchip wiring consists of a single or a multi-level grid of wire segments 3 (Fig. 2) on the wiring wafer. The wire segments may be implemented as metal conductor strips, polysilicon type material or even as optical links.

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Logically Controlled Chip Interconnection Technique

A silicon wiring wafer 1 is used as a carrier for chips 2 and as a chip interconnection means (Fig. 1). The interchip wiring consists of a single or a multi-level grid of wire segments 3 (Fig. 2) on the wiring wafer. The wire segments may be implemented as metal conductor strips, polysilicon type material or even as optical links.

At the ends of wire segments 3, semiconductor switches 4, such as transfer devices in FET technology, are provided (Fig. 3) which permit interconnecting the wire segments 3 and the chip pads. Switches 4 may be dynamically activated for a specific interconnection pattern by master/slave latches 5 located in the wiring wafer. Latches 5 control switches 4 connecting the individual wire segments 3 and may be set by known scan/set mechanisms (such as LSSD or RAS) on request. There

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fore, this interconnection technique is universally applicable. Personalization of the interconnection is determined by the specific system interconnection or configuration requirements and may be accomplished by the system controller, say, the service processor. Thus, this interconnection is reversible. The system controller itself may be a chip 2 or part of such a chip on silicon carrier 1.

The system controller may also be used to configure the system according to customer requirements. Depending upon the respective application, a graphics chip II (not shown) may be invoked instead of a graphics chip I (not shown either) by activating the connections of wire segment 3. The same holds for other units, such as memory extensions, reconfiguration as a result of memory and/or logic chip defects, etc., or deconfiguration of a defective processor in a multiprocessor environment. This highly flexible dynamic interconnection of chips 2 may be used to advantage for system implementations based on standard vendor parts.

The advantage of dynamic interconnection may also be utilized for a CPU connected to a bus with several I/O units. In such a case, the CPU drivers can be directly connected to only one I/O unit at a time, thus significantly reducing the load on the drivers and equally significantly increasing the speed of this interface. Switches 4 (transfer devices) are directly controlled by the bus arbitration logic for the required time.

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A wiring grid or matrix is shown in Fig. 2A. Adjacent ends of wire segments 3 make up a wiring node 6. In order to flexibly utilize all wire segments 3, six switches 4 with the associated control latches 5 are required (Fig. 2B). According to Fig. 3, the number of switches and associated latches is reduced to three, without sacrificing interconnection flexibility. In some cases, only one adjacent wire segment must be used as a stub and thus is not available for another independent interconnection. The solution with only three switches requires less hardware and the wire segments may be located on a single metallization la...