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# High Resolution Digital Phase Detector

IP.com Disclosure Number: IPCOM000035979D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 52K

IBM

## Related People

Chang, PT: AUTHOR [+2]

## Abstract

This article describes a method for precise alignment of two digital timing edges. A counter is used to average out the effects of edge jitter, thereby increasing the alignment accuracy.

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High Resolution Digital Phase Detector

This article describes a method for precise alignment of two digital timing edges. A counter is used to average out the effects of edge jitter, thereby increasing the alignment accuracy.

As shown in Fig. 1, a D flip-flop FF1 is used as a simple digital phase detector. Its output Q will be a logic 1 if the rising edge of Input 1 occurs before the rising edge of Input 2 or a logic 0 if Input

(Image Omitted)

1 is after Input 2. When Input 1 and Input 2 occur at the same time, the Q output will not be a steady 1 or 0 but will sometimes be a 1 and sometimes be a 0. When the number of 1s equals the number of 0s (within some tolerance), the two edges are "perfectly" aligned.

The Q output from FF1 is used to enable or disable an N bit Counter which is also clocked by Input 2. This counter will count the number of times that Q was a
1. This is the same as saying that the counter counts the number of times that Input 1 is ahead of Input 2.

An N bit Latch is used to latch the N bit of output from the counter when clocked by the Control Logic. The output of the latch is an N bit binary number Nc which represents the amount of phase difference between Input 1 and Input 2:
Nc = 0 Input 1 leads Input 2
Nc = 2N - 1 Input 1 lags Input 2 0 < Nc < 2N - 1 The two inputs are nearly aligned. Due to edge

jitter, sometimes Input 1 leads,

sometimes Input 2